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december 1990 order number: 271029-005 m80287 80-bit hmos * numeric processor extension military y high performance 80-bit internal architecture y implements proposed ieee floating point standard 754 y expands m80286/10 datatypes to include 32-, 64-, 80-bit floating point, 32-, 64-bit integers and 18-digit bcd operands y object code compatible with m8087 y built-in exception handling y operates in both real and protected mode m80286 systems y available in a 40-pin cerdip package y protected mode operation completely conforms to the m80286 memory management and protection mechanisms y directly extends m80286/10 instruction set to trigonometric, logarithmic, exponential and arithmetic instructions for all datatypes y 8 x 80-bit, individually addressable, numeric register stack y 6, 8, 10 mhz y military temperature range: b 55 cto a 125 c(t c ) the intel m80287 is a high performance numerics processor extension that extends the m80286/10 architec- ture with floating point, extended integer and bcd data types. the m80286/20 computing system (m80286 and m80287) fully conforms to the proposed ieee floating point standard. using a numerics oriented archi- tecture, the m80287 adds over fifty mnemonics to the m80286/20 instruction set, making the m80286/20 a complete solution for high performance numeric processing. the m80287 is implemented in n-channel, deple- tion load, silicon gate technology (hmos) and packaged in a 40-pin ceramic package. the m80286/20 is object code compatible with the m80286/20 and m8088/20. intel's hmos iii process provides superior radiation tolerance for applications with stringent radiation requirements. * hmos is a patented process of intel corporation. 271029 1 figure 1. m80287 block diagram 271029 2 note: n.c. pins must not be connected. figure 2. m80287 pin configuration
m80287 table 1. m80287 pin description symbol type name and function clk i clock input: this clock provides the basic timing for internal m80287 operations. special mos level inputs are required. the m82284 or m8284a clk outputs are compatible to this input. ckm i clock mode signal: indicates whether clk input is to be divided by 3 or used directly. a high input will select the latter option. this input may be connected to v cc or v ss as appropriate. this input must be either high or low 20 clk cycles before reset goes low. reset i system reset: causes the m80287 to immediately terminate its present activity and enter a dormant state. reset is required to be high for more than 4 m80287 clk cycles. for proper initialization the high-low transition must occur no sooner than 50 m s after v cc and clk meet their d.c. and a.c. specifications. d15 d0 i/o data: 16-bit bidirectional data bus. inputs to these pins may be applied asynchronous to the m80287 clock. busy o busy status: asserted by the m80287 to indicate that it is currently executing a command. error o error status: reflects the es bit of the status word. this signal indicates that an unmasked error condition exists. pereq o processor extension data channel operand transfer request: a high on this output indicates that the m80287 is ready to transfer data. pereq will be disabled upon assertion of peack or upon actual data transfer, whichever occurs first, if no more transfers are required. peack i processor extension data channel operand transfer acknowledge: acknowledges that the request signal (pereq) has been recognized. will cause the request (pereq) to be withdrawn in case there are no more transfers required. peack may be asynchronous to the m80287 clock. nprd i numeric processor read: enables transfer of data from the m80287. this input may be asynchronous to the m80287 clock. npwr i numeric processor write: enables transfer of data to the m80287. this input may be asynchronous to the m80287 clock. nps1 , nps2 i numeric processor selects: indicates the cpu is performing an escape instruction. concurrent assertion of these signals (i.e., nps1 is low and nps2 is high) enables the m80287 to perform floating point instructions. no data transfers involving the m80287 will occur unless the device is selected via these lines. these inputs may be asynchronous to the m80287 clock. cmd1, cmd0 i command lines: these, along with select inputs, allow the cpu to direct the operation of the m80287. no actions will occur if these signals are both high. these inputs may be asynchronous to the m80287 clock. clk286 i cpu clock: this input provides a sampling edge for the m80287 inputs s1 ,s0 , cod/inta , ready , and hlda. it must be connected to the m80286 clk input. s1 ,s0 i status: these inputs allow the m80287 to monitor the execution of cod/inta escape instructions by the m80286. they must be connected to the corresponding m80286 pins. hlda i hold acknowledge: this input informs the m80287 when the m80286 controls the local bus. it must be connected to the m80286 hlda output. ready i ready: the end of a bus cycle is signaled by this input. it must be connected to the m80286 ready input. v ss i ground: system ground, both pins must be connected to ground. v cc i power: a 5v supply. 2
m80287 functional description the m80287 numeric processor extension (npx) provides arithmetic instructions for a variety of nu- meric data types in m80286/20 systems. it also exe- cutes numerous built-in transcendental functions (e.g., tangent and log functions). the m80287 exe- cutes instructions in parallel with an m80286. it ef- fectively extends the register and instruction set of an m80286/10 system for existing m80286 data types and adds several new data types as well. fig- ure 3 presents the program visible register model of the m80286/20. essentially, the m80287 can be treated as an additional resource or an extension to the m80286/10 that can be used as a single unified system, the m80286/20. the m80287 has two operating modes similar to the two modes of the m80286. when reset, m80287 is in the real address mode. it can be placed in the pro- tected virtual address mode by executing the setpm esc instruction. the m80287 cannot be switched back to the real address mode except by reset. in the real address mode, the m80286/20 is completely software compatible with m8086, 88/20. once in protected mode, all references to memory for numerics data or status information, obey the m80286 memory management and protection rules giving a fully protected extension of the m80286 cpu. in the protected mode, m80286/20 numerics software is also completely compatible with m8086/20 and m8088/20. the m80287 has two operating modes similar to the two modes of the m80286. when reset, m80287 is in the real address mode. it can be placed in the protected virtual address mode by executing the setpm esc instruction. the m80287 cannot be switched back to the real address mode except by reset. in the real address mode, the m80286/m80287 is completely software compatible with m8086/m8087 and m8088/m8087. once in protected mode, all references to memory for numerics data or status information, obey the m80286 memory management and protection rules giving a fully protected extension of the m80286 cpu. in the protected mode, m80286/m80287 nu- merics software is also completely compatible with m8086/m8087 and m8088/m8087. 271029 3 figure 3. m80286/20 architecture 3
m80287 absolute maximum ratings * storage temperature under bias b 65 cto a 150 c case temperature b 55 cto a 125 c voltage on any pin with respect to ground b 1.0 to a 7v power dissipation 3.0 watt notice: this is a production data sheet. the specifi- cations are subject to change without notice. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. operating conditions symbol description min max units t c case temperature (instant on) b 55 a 125 c v cc digital supply voltage 4.75 5.25 v d.c. characteristics (over specified operating conditions) symbol parameter min max unit test conditions v il input low voltage b 0.5 0.8 v v ih input high voltage 2.0 v cc a 0.5 v v ilc clock input low voltage ckm e 1: 2.0 v cc a 1v ckm e 0: 3.8 v cc a 1v v ol output low voltage 0.45 v i ol e 3.0 ma v oh output high voltage 2.4 v i oh eb 400 m a i li input leakage current g 10 m a0v s v in s v cc i lo output leakage current g 10 m a 0.45v s v out s v cc i cc power supply current 600 ma t c eb 55 c c in input capacitance 10 pf f c e 1 mhz c o input/output capacitance 20 pf f c e 1 mhz (d0 d15) c clk clk capacitance 12 pf f c e 1 mhz 4
m80287 a.c. characteristics (over specified operating conditions) timing requirements a.c. timings are referenced to 0.8v and 2.0v points on signals unless otherwise noted. symbol parameter 6 mhz 8 mhz 10 mhz unit comments -6 min -6 max -8 min -8 max -10 min -10 max t clcl clk period ckm e 1 165 500 125 500 100 500 ns ckm e 0 62.5 166 50 166 40 166 ns t clch clk low time ckm e 1 100 343 68 343 53 343 ns at 0.8v ckm e 0 15 146 15 146 11 146 ns at 0.6v t chcl clk high time ckm e 1 50 230 43 230 28 230 ns at 2.0v ckm e 0 20 151 20 151 18 151 ns at 3.6v t ch1ch2 clk rise time 10 10 10 ns 1.0v to 3.6v if ckm e 1 t cl2cl1 clk fall time 10 10 10 ns 3.6v to 1.0v if ckm e 1 t dvwh data setup to npwr inactive 75 75 75 ns t whdx data hold from npwr inactive 30 18 18 ns t wlwh npwr nprd active time 95 90 90 ns at 0.8v t rlrh t avrl command valid to npwr or 0 0 0 ns t avwl nprd active t mhrl minimum delay from pereq 130 130 100 ns active to nprd active t klkh peak active time 85 85 60 ns at 0.8v t khkl peak inactive time 250 250 200 ns at 2.0v t khch peak inactive to npwr ,50 40 40 ns nprd inactive t chkl npwr nprd inactive to b 30 b 30 b 30 ns peak inactive t whax command hold from npwr 30 30 22 ns t rhax nprd inactive t klcl peak active setup to npwr 50 40 40 ns nprd active t ivcl npwr , nprd , reset 70 70 53 ns to clk setup time t clih npwr, nprd , reset 45 45 37 ns from clk hold time t rscl reset to clk setup time 20 20 20 ns t clrs reset from clk hold time 20 20 20 ns note: t ja e 41 c/w t jc e 14 c/w 5
m80287 a.c. characteristics (over specified operating conditions) timing responses symbol parameter 6 mhz 8 mhz 10 mhz unit comments -6 min -6 max -8 min -8 max -10 min -10 max t rhqz nprd inactive to data float 37.5 35 25 ns (note 2) t rlqv nprd active to data valid 60 60 60 ns (note 3) t ilbh error active to busy 100 100 100 ns (note 4) inactive t wlbv npwr active to busy active 100 100 100 ns (note 5) t klml peack active to pereq 127 127 127 ns (note 6) inactive t cmdi command inactive time write-to-write 95 95 75 ns at 2.0v read-to-read 95 95 75 ns at 2.0v write-to-read 95 95 75 ns at 2.0v read-to-write 95 95 75 ns at 2.0v t rhch data hold from nprd 3 3 3 ns (note 7) inactive notes: 2. float condition occurs when output current is less than i lo on d0 d15. 3. d0 d15 loading: cl e 100 pf. 4. busy loading: cl e 100 pf. 5. busy loading: cl e 100 pf. 6. on last data transfer of numeric instruction. 7. d0 d15 loading: cl e 100 pf. 6
m80287 waveforms data transfer timing (initiated by m80286) 271029 16 data channel timing (initiated by m80287) 271029 17 7
m80287 waveforms (continued) error output timing 271029 18 clk, reset timing (ckm e 1) 271029 19 note: reset, npwr , nprd are inputs asynchronous to clk. timing requirements for reset, npwr , and nprd are given for testing purposes only, to assure recognition at a specific clk edge. 8
m80287 waveforms (continued) clk, nprd , npwr timing (ckm e 1) 271029 20 clk, reset timing (ckm e 0) 271029 21 note: reset must meet timing shown to guarantee known phase of internal d 3 circuit. clk, nprd , npwr timing (ckm e 0) 271029 22 note: reset, npwr , nprd are inputs asynchronous to clk. timing requirements for reset, npwr , and nprd are given for testing purposes only, to assure recognition at a specific clk edge. 9
m80287 waveforms (continued) 271029 23 ac drive and measurement pointseclk input 271029 24 ac setup, hold and delay time measurementegeneral 271029 25 ac test loading on outputs 10
m80287 system configuration with m80286 as a processor extension to an m80286, the m80287 can be connected to the cpu as shown in figure 4. the data channel control signals (pereq, peack ), the busy signal and the nprd , npwr signals, allow the npx to receive instructions and data from the cpu. when in the protected mode, all information received by the npx is validated by the m80286 memory management and protection unit. once started, the m80287 can process in parallel with and independent of the host cpu. when the npx detects an error or exception, it will indicate this to the cpu by asserting the error signal. the npx uses the processor extension request and acknowledge pins of the m80286 cpu to implement data transfers with memory under the protection model of the cpu. the full virtual and physical ad- dress space of the m80286 is available. data for the m80287 in memory is addressed and represented in the same manner as for an m8087. the m80287 can operate either directly from the cpu clock or with a dedicated clock. for operation with the cpu clock (ckm e 0), the m80287 works at one-third the frequency of the system clock (i.e., for an 8 mhz m80286, the 16 mhz system clock is divided down to 5.3 mhz). the m80287 provides a capability to internally divide the cpu clock by three to produce the required internal clock (33% duty cy- cle). to use a higher performance m80287 (8 mhz), an m8284a clock driver and appropriate crystal may be used to directly drive the m80287 with a (/3 duty cycle clock on the clk input (ckm e 1). system configuration with m80386 the m80287 can also be connected as a processor extension to the m80386 cpu as shown in figure 4b. all software written for m8086/m8087 and m80286/m80287 is object code compatible with 80386/m80287 and can benefit from the increased speed of the m80386 cpu. note that the peack input pin is pulled high. this is because the m80287 is not required to keep track of the number of words transferred during an operand transfer when it is connected to the m80386 cpu. unlike the m80286 cpu, the m80386 cpu knows the exact length of the operand being transferred to/from the m80287. after an esc instruction has been sent to the m80287, the m80386 processor extension data channel will initiate the data transfer as soon as it receives the pereq signal from the m80287. the transfer is automatically terminated by the m80386 cpu as soon as all the words of the operand have been transferred. because of the very high speed local bus of the m80386 cpu, the m80287 cannot reside directly on the cpu local bus. a local bus controller logic is used to generate the necessary read and write cycle timing as well as the chip select timings for the m80287. the m80386 cpu uses i/o addresses 800000f8 through 800000ff to communicate with the m80287. this is beyond the normal i/o address space of the cpu and makes it easier to generate the chip select signals using a31 and m/io .itmay also be noted that the m80386 cpu automatically generates 16-bit bus cycles whenever it communi- cates with the m80287. hardware interface communication of instructions and data operands between the m80286 and m80287 is handled by the cmd0, cmd1, nps1 , nps2, nprd , and npwr sig- nals. i/o port addresses 00f8h, 00fah, and 00fch are used by the m80286 for this communication. when any of these addresses are used, the nps1 input must be low and nps2 input high. the iorc and iowc outputs of the m82288 identify i/o space transfers (see figure 4). cmd0 should be connected to latched m80286 a1 and cmd1 should be connected to latched m80286 a2. i/o ports 00f8h to 00ffh are reserved for the m80286/m80287 interface. to guarantee correct operation of the m80287, programs must not per- form any i/o operations to these ports. the pereq, peack , busy , and error signals of the m80287 are connected to the same-named m80286 input. the data pins of the m80287 should be directly connected to the m80286 data bus. note that all bus drivers connected to the m80286 local bus must be inhibited when the m80286 reads from the m80287. the use of cod/inta and m/io in the decoder prevents inta bus cycles from disabling the data transceivers. the s1 ,s0 , cod/inta , ready , hlda, and clk pins of the m80286 are connected to the same named pins on the m80287. these signals allow the m80287 to monitor the execution of escape in- structions by the m80826. programming interface table 2 lists the seven data types the m80287 sup- ports and presents the format for each type. these values are stored in memory with the least signifi- cant digits at the lowest memory address. programs retrieve these values by generating the lowest ad- dress. all values should start at even addresses for maximum system performance. 11
m80287 271029 4 figure 4. m80286/20 system configuration internally the m80287 holds all numbers in the tem- porary real format. load instructions automatically convert operands represented in memory as 16-, 32-, or 64-bit integers, 32- or 64-bit floating point numbers or 18-digit packed bcd numbers into tem- porary real format. store instructions perform the re- verse type conversion. m80287 computations use the processor's register stack. these eight 80-bit registers provide the equiv- alent capacity of 40 16-bit registers. the m80287 register set can be accessed as a stack, with in- structions operating on the top one or two stack ele- ments, or as a fixed register set, with instructions operating on explicitly designated registers. table 6 lists the m80287's instructions by class. no special programming tools are necessary to use the m80287 since all new instructions and data types are directly supported by the m80286 assembler and appropriate high level languages. all m8086/88 de- velopment tools which support the m8087 can also be used to develop software for the m80286 in real address mode. table 3 gives the execution times of some typical numeric instructions. 12
m80287 table 2. m80287 datatype representation in memory 271029 5 notes: 1. s e sign bit (0 e positive, 1 e negative) 2. d n e decimal digit (two per byte) 3. x e bits have no significance; m8087 ignores when loading, zeros when storing. 4. u e position of implicit binary point 5. i e integer bit of significand; stored in temporary real, implicit in short and long real. 6. exponent bias (normalized values): short real: 127 (7fh) long real: 1023 (3ffh) temporary real: 16383 (3fffh) 7. packed bcd: ( b 1) s (d 17 ...d 0 ) 8. real: ( b 1) s (2 e-bias )(f 0 f 1 ...) software interface the m80286/20 is programmed as a single proces- sor. all communication between the m80286 and the m80287 is transparent to software. the cpu au- tomatically controls the m80287 whenever a numer- ic instruction is executed. all memory addressing modes, physical memory, and virtual memory of the cpu are available for use by the npx. since the npx operates in parallel with the cpu, any errors detected by the npx may be reported after the cpu has executed the escape instruction which caused it. to allow identification of the failing numeric instruction, the npx contains two pointer registers which identify the address of the failing nu- meric instruction and the numeric memory operand if appropriate for the instruction encountering this er- ror. 13
m80287 table 3. execution time for selected m80287 instructions approximate execution floating point instruction time ( m s) m80287 (5 mhz operation) add/subtract 14/18 multiply (single precision) 19 multiply (extended precision) 27 divide 39 compare 9 load (double precision) 10 store (double precision) 21 square root 36 tangent 90 exponentiation 100 interrupt description several interrupts of the m80286 are used to report exceptional conditions while executing numeric pro- grams in either real or protected mode. the inter- rupts and their functions are shown in table 4. processor architecture as shown in figure 1, the npx is internally divided into two processing elements, the bus interface unit (biu) and the numeric execution unit (neu). the neu executes all numeric instructions, while the biu receives and decodes instructions, requests oper- and transfers to and from memory and executes processor control instructions. the two units are able to operate independently of one another allow- ing the biu to maintain asynchronous communica- tion with the cpu while the neu is busy processing a numeric instruction. bus interface unit the biu decodes the esc instruction executed by the cpu. if the esc code defines a math instruction, the biu transmits the formatted instruction to the neu. if the esc code defines an administrative in- struction, the biu executes it independently of the neu. the parallel operation of the npx with the cpu is normally transparent to the user. the biu generates the busy and error signals for m80286/m80287 processor synchronization, and error notification, respectively. the m80287 executes a single numeric instruction at a time. when executing most esc instructions, the m80286 tests the busy pin and waits until the m80287 indicates that it is not busy before initiating the command. once initiated, the m80286 continues program execution while the m80287 executes the esc instruction. in m8086/20 systems, this synchro- nization is achieved by placing a wait instruction before an esc instruction. for most esc instruc- tions, the m80286/20 does not require a wait in- struction before the esc opcode. however, the m80286/20 will operate correctly with these wait instructions. in all cases, a wait or esc instruction should be inserted after any m80287 store to memo- ry (except fstsw and fstcw) or load from memo- ry (except fldenv or frstor) before the m80286 reads or changes the value. data transfers between memory and the m80287, when needed, are controlled by the pereq, peack , nprd , npwr , nps1 , nps2 signals. the m80286 does the actual data transfer with memory through its processor extension data channel. nu- meric data transfers with memory performed by the m80286 use the same timing as any other bus cycle. control signals for the m80287 are generated by the m80286 as shown in figure 4, and meet the timing requirements shown in the ac requirements section. 14
m80287 table 4. interrupt vectors interrupt number interrupt function 7 an esc instruction was encountered when em or ts of the m80286 msw was set. em e 1 indicates that software emulation of the instruction is required. when ts is set, either an esc or wait instruction will cause interrupt 7. this indicates that the current npx context may not belong to the current task. 9 the second or subsequent words of a numeric operand in memory exceeded a segment's limit. this interrupt occurs after executing an esc instruction. the saved return address will not point at the numeric instruction causing this interrupt. after processing the addressing error, the m80286 program can be restarted at the return address with iret. the address of the failing numeric instruction and numeric operand are saved in the m80287. an interrupt handler for this interrupt must execute fninit before any other esc or wait instruction. 13 the starting address of a numeric operand is not in the segment's limit. the return address will point at the esc instruction (including prefixes) causing this error. the m80287 has not executed this instruction. the instruction and data address in m80287 refer to a previous, correctly executed, instruction. 16 the previous numeric instruction caused an unmasked numeric error. the address of the faulty numeric instruction or numeric data operand is stored in the m80287. only esc or wait instructions can cause this interrupt. the m80286 return address will point at a wait or esc instruction, including prefixes, which may be restarted after clearing the error condition in the npx. numeric execution unit the neu executes all instructions that involve the register stack; these include arithmetic, logical, tran- scendental, constant and data transfer instructions. the data path in the neu is 84 bits wide (68 fraction bits, 15 exponent bits and a sign bit) which allows internal operand transfers to be performed at very high speeds. when the neu begins executing an instruction, it activates the biu busy signal. this signal is used in conjunction with the cpu wait instruction or auto- matically with most of the esc instructions to syn- chronize both processors. register set the m80287 register set is shown in figure 5. each of the eight data registers in the m8087's register stack is 80 bits wide and is divided into ``fields'' cor- responding to the npx's temporary real data type. at a given point in time the top field in the status word identifies the current top-of-stack register. a ``push'' operation decrements top by 1 and loads a value into the new top register. a ``pop'' operation stores the value from the current top register and then increments top by 1. like m80286 stacks in memory, the m80287 register stack grows ``down'' toward lower-addressed registers. instructions may address the data registers either implicitly or explicitly. many instructions operate on the register at the top of the stack. these instruc- tions implicitly address the register pointed by the top. other instructions allow the programmer to ex- plicitly specify the register which is to be used. ex- plicit register addressing is ``top-relative.'' status word the 16-bit status word (in the status register) shown in figure 6 reflects the overall state of the m80287. it may be read and inspected by cpu code. the busy bit (bit 15) indicates whether the neu is exe- cuting an instruction (b e 1) or is idle (b e 0). the instructions fstsw, fstenv, fstswax and fsave which store the status word are executed exclusively by the biu and do not set the busy bit themselves or require the busy bit be cleared in or- der to be executed. the four numeric condition code bits (c 0 c 3 ) are similar to the flags in a cpu: instructions that per- form arithmetic operations update these bits to re- flect the outcome of ndp operations. the effect of these instructions on the condition code bits is sum- marized in tables 5a and 5b. 15
m80287 271029 11 figure 5. m80287 register set 271029 6 notes: 1. es is set if any unmasked exception bit is set, cleared otherwise. 2. see table 5 for condition code interpretation. 3. top values 000 e register 0 is top of stack 001 e register 1 is top of stack # # # 111 e register 7 is top of stack * for definitions, see the section on exception handling. figure 6. m80287 status word 16
m80287 bits 14 12 of the status word point to the m80287 register that is the current top-of-stack (top) as de- scribed above. figure 6 shows the six error flags in bits 5 0 of the status word. bits 5 0 are set to indi- cate that the neu has detected an exception while executing an instruction. the section on exception handling explains how they are set and used. bit 7 is the error status bit. this bit is set if any un- masked exception bit is set and cleared otherwise. if this bit is set, the error signal is asserted. tag word the tag word marks the content of each register as shown in figure 7. the principal function of the tag word is to optimize the npx's performance. the tag word can be used, however, to interpret the con- tents of m80287 registers. instruction and data pointers the instruction and data pointers (see figures 8a and 8b) are provided for user-written error handlers. whenever the m80287 executes a new instruction, the biu saves the instruction address, the operand address (if present) and the instruction opcode. m80287 instructions can store this data into memo- ry. the instruction and data pointers appear in one of two formats depending on the operating mode of the m80287. in real mode, these values are the 20-bit physical address and 11-bit opcode formatted like the m8087. in protected mode, these values are the 32-bit virtual addresses used by the program which executed an esc instruction. the same fldenv/ fstenv/fsave/frstor instructions as those of the m8087 are used to transfer these values be- tween the m80287 registers and memory. table 5a. condition code interpretation instruction c 3 c 2 c 1 c 0 interpretation type compare, test 0 0 x 0 st l source or 0 (ftst) 00x1st k source or 0 (ftst) 10x0st e source or 0 (ftst) 1 1 x 1 st is not comparable remainder q 1 0q 0 q 2 complete reduction with three low bits of quotient (see table 5b) u 1 u u incomplete reduction examine 0 0 0 0 valid, positive unnormalized 0 0 0 1 invalid, positive, exponent e 0 0 0 1 0 valid, negative, unnormalized 0 0 1 1 invalid, negative, exponent e 0 0 1 0 0 valid, positive, normalized 0 1 0 1 infinity, positive 0 1 1 0 valid, negative, normalized 0 1 1 1 infinity, negative 1 0 0 0 zero, positive 1 0 0 1 empty 1 0 1 0 zero, negative 1 0 1 1 empty 1 1 0 0 invalid, positive, exponent e 0 1 1 0 1 empty 1 1 1 0 invalid, negative, exponent e 0 1 1 1 1 empty notes: 1. st e top of stack 2. x e value is not affected by instruction 3. u e value is undefined following instruction 4. q n e quotient bit n 17
m80287 271029 12 note: the index i of tag(i) is not top-relative. a program typically uses the ``top'' field of status word to determine which tag(i) field refers to logical top of stack. figure 7. m80287 tag word table 5b. condition code interpretation after fprem instruction as a function of dividend value dividend range q 2 q 1 q 0 dividend k 2 * modulus c 3 c 1 q 0 dividend k 4 * modulus c 3 q 1 q 0 dividend t 4 * modulus q 2 q 1 q 0 note: 1. previous value of indicated bit, not affected by fprem instruction execution. the saved instruction address in the m80287 will point at any prefixes which preceded the instruction. this is different than in the m8087 which only point- ed at the escape instruction opcode. control word the npx provides several processing options which are selected by loading a word from memory into the control word. figure 9 shows the format and encod- ing of fields in the control word. the low order byte of this control word configures the m80287 error and exception masking. bits 5 0 of the control word contain individual masks for each of the six exceptions that the m80287 recognizes. the high order byte of the control word configures the m80287 operating mode including precision, rounding, and infinity control. the precision control bits (bits 9 8) can be used to set the m80287 inter- nal operating precision at less than the default of temporary real (80-bit) precision. this can be useful in providing compatibility with the early generation arithmetic processors of smaller precision than the m80287. the rounding control bits (bits 11 10) pro- vide for directed rounding and true chop as well as the unbiased round to nearest even mode specified in the ieee standard. control over closure of the number space at infinity is also provided (either af- fine closure: g % , or projective closure: % , is treat- ed as unsigned, may be specified). exception handling the m80287 detects six different exception condi- tions that can occur during instruction execution. any or all exceptions will cause the assertion of error signal if the appropriate exception masks are not set. the exceptions that the m80287 detects and the `default' procedures that will be carried out if the ex- ception is masked, are as follows: invalid operation: stack overflow, stack underflow, indeterminate form (0/0, % % , etc.) or the use of a non-number (nan) as an operand. an exponent value of all ones and non-zero significand is re- served to identify nans. if this exception is masked, the m80287 default response is to generate a spe- cific nan called indefinite, or to propagate al- ready existing nans as the calculation result. overflow: the result is too large in magnitude to fit the specified format. the m80287 will generate an encoding for infinity if this exception is masked. zero divisor: the divisor is zero while the dividend is a non-infinite, non-zero number. again, the m80287 will generate an encoding for infinity if this exception is masked. underflow: the result is non-zero but too small in magnitude to fit in the specified format. if this excep- tion is masked the m82087 will denormalize (shift right) the fraction until the exponent is in range. the process is called gradual underflow. 18
m80287 271029 13 figure 8a. protected mode instruction and data pointer image in memory denormalized operand: at least one of the oper- ands is denormalized; it has the smallest exponent but a non-zero significand. normal processing con- tinues if this exception is masked off. inexact result: if the true result is not exactly repre- sentable in the specified format, the result is round- ed according to the rounding mode, and this flag is set. if this exception is masked, processing will sim- ply continue. if the error is not masked, the corresponding error bit and the error status bit (es) in the control word will be set, and the error output signal will be as- serted. if the cpu attempts to execute another esc or wait instruction, exception 7 will occur. the error condition must be resolved via an interrupt service routine. the m80287 saves the address of the floating point instruction causing the error as well as the address of the lowest memory location of any memory operand required by that instruction. m8086/20 compatibility m80286/20 supports portability of m8086/20 pro- grams when it is in the real address mode. however, because of differences in the numeric error handling techniques, error handling routines may need to be changed. the differences between an m80286/20 and m8086/20 are: 1. the npx error signal does not pass through an interrupt controller (m8087 int signal does). therefore, any interrupt controller oriented instruc- tions for the m8086/20 may have to be deleted. 2. interrupt vector 16 must point at the numeric error handler routine. 3. the saved floating point instruction address in the m80287 includes any leading prefixes before the escape opcode. the corresponding saved address of the m8087 does not include leading prefixes. 4. in protected mode, the format of the saved in- struction and operand pointers is different than for the m8087. the instruction opcode is not savedeit must be read from memory if needed. 5. interrupt 7 will occur when executing esc instruc- tions with either ts or em of msw e 1. if ts of msw e 1 then wait will also cause interrupt 7. an interrupt handler should be added to handle this situ- ation. 6. interrupt 9 will occur if the second or subsequent words of a floating point operand fall outside a seg- ment's size. interrupt 13 will occur if the starting ad- dress of a numeric operand falls outside a seg- ment's size. an interrupt handler should be added to report these programming errors. in the protected mode, m8086/20 application code can be directly ported via recompilation if the 286 memory protection rules are not violated. 19
m80287 271029 14 figure 8b. real mode m80287 instruction and data pointer image in memory 271029 7 notes: 1. precision control 2. rounding control 00 e 24 bits (short real) 00 e round to nearest or even 01 e reserved 01 e round down (toward b % ) 10 e 53 bits (long real) 10 e round up (toward a % ) 11 e 64 bits (temp real) 11 e chop (truncate toward zero) figure 9. m80287 control word 20
m80287 table 6. m80287 extensions to the m80286 instruction set mnemonics ? intel 1982. 271029 8 21
m80287 table 6. m80287 extensions to the m80286 instruction set (continued) 271029 9 note: 1. if p e 1 then add 5 clocks. 22
m80287 table 6. m80287 extensions to the m80286 instruction set (continued) 271029 10 23
m80287 table 6. m80287 extensions to the m80286 instruction set (continued) 271029 15 notes: 1. if mod e 00 then disp e 0 * , disp-low and disp-high are absent if mod e 01 then disp e disp-low sign-extended to 16-bits, disp-high is absent if mod e 10 then disp e disp-high; disp-low if mod e 11 then r/m is treated as an st(i) field 2. if r/m e 000 then ea e (bx) a (si) a disp if r/m e 001 then ea e (bx) a (di) a disp if r/m e 010 then ea e (bp) a (si) a disp if r/m e 011 then ea e (bp) a (di) a disp if r/m e 100 then ea e (si) a disp if r/m e 101 then ea e (di) a disp if r/m e 110 then ea e (bp) a disp if r/m e 111 then ea e (bx) a disp * except if mod e 000 and r/m e 110 then ea e disp-high; disp-low. 3. mf e memory format 00e32-bit real 01e32-bit integer 10e64-bit real 11e16-bit integer 4. st(0) e current stack top st(i) i th register below stack top 5. d e destination 0edestination is st(0) 1edestination is st(i) 6. p e pop 0eno pop 1epop st(0) 7. r e reverse: when d e 1 reverse the sense of r 0edestination (op) source 1esource (op) destination 8. for fsqrt: b 0 s st(0) s a % for fscale: b 2 15 s st(1) k a 2 15 and st(1) integer for f2xm1: 0 s st(0) s 2 b 1 for fyl2x: 0 k st(0) k % b % k st(1) k a % for fyl2xp1: 0 s ist(0)i k (2 b s 2)/2 b % k st(1) k % for fptan: 0 s st(0) s q /4 for fpatan: 0 s st(0) k st(1) k a % 9. escape bit pattern is 11011. intel corporation, 2200 mission college blvd., santa clara, ca 95052; tel. (408) 765-8080 intel corporation (u.k.) ltd., swindon, united kingdom; tel. (0793) 696 000 intel japan k.k., ibaraki-ken; tel. 029747-8511 printed in u.s.a./xxxx/1296/2.5k/rp sm military operation

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